Exemplary embodiments of the present invention relate to a semiconductor device design technology, and more particularly, to a semiconductor memory device which programs data by using a programming voltage.
In general, semiconductor memory devices are divided into volatile memory devices such as Dynamic Random Access Memory
(DRAM) devices and Static Random Access Memory (SRAM) devices, and into non-volatile memory devices such as Programmable Read Only Memory (PROM), Erasable PROM (EPROM), Electrically EPROM (EEPROM), and flash memory devices.
The main difference between volatile memory devices and non-volatile memory devices is whether the memory device sustains a data after a predetermined time passes.
In other words, whereas the volatile memory device does not sustain data after a predetermined time passes, the non-volatile memory device does sustain data even after a predetermined time passes. Therefore, volatile memory devices perform a refresh operation to preserve data, while non-volatile memory devices do not perform the refresh operation. Since non-volatile memory devices are appropriate for low-voltage and high-integration purposes, they are widely used as a storage medium for storing data.
Meanwhile, flash memory device, which is a kind of non-volatile memory device, includes a plurality of memory cells for storing data. The plurality of memory cells are serially coupled with each other so as to form a string structure.
In a write operation, the flash memory device performs a program operation and an erase operation. The flash memory device stores data in the memory cells through the program operation and the erase operation. Herein, the program operation is an operation for accumulating electrons in a floating gate of a transistor that forms a memory cell.
The erase operation is an operation for discharging the electrons accumulated in the floating gate to a substrate. The flash memory device stores data of ‘0’ or ‘1’ in a memory cell through the aforementioned operations, detects the amount of electrons accumulated in the floating gate during a read operation, and outputs data of ‘0’ or ‘1’ based on the detection result.
Meanwhile, as described earlier, one memory cell stores data of ‘0’ or ‘1’. In other words, one memory cell stores one bit of data, and the memory cell is referred to as a single-level cell (SLC).
Recently, a scheme of storing more than one bit of data in one memory cell has been adopted, and this kind of memory cell is referred to as a multi-level cell (MLC). The single-level cell requires a single threshold voltage to determine whether data of ‘0’ or ‘1’ is stored in the memory cell. On the other hand, the multi-level cell requires multiple threshold voltages to determine which data, for example, ‘00,’ ‘01,’ ‘10,’ or ‘11,’ is stored in the memory cell.
Accordingly, a semiconductor memory device uses an Incremental Step Pulse Program (ISPP) to give memory cells a predetermined distribution. Herein, the ISPP is a method of programming a memory cell by using a pulse having a voltage that is increased step by step from a predetermined starting voltage. The memory cell programs a desired data based on the programming voltage having the above-described pulse.
FIG. 1 illustrates a relationship between temperature and a threshold voltage distribution when a semiconductor memory device operates. For the sake of convenience in description, a threshold voltage set up in a hot temperature condition is referred to as a first deciding voltage V_VF1, and a threshold voltage set up in a cold temperature condition is referred to as a second deciding voltage V_VF2.
Referring to FIG. 1, a distribution of memory cells in a hot temperature condition and a distribution of memory cells in a cold temperature condition are shown for the same data. Generally, a semiconductor memory device has its operation characteristics varying according to temperature. As shown in FIG. 1, the memory cells are affected by temperature as well.
In other words, the threshold voltage value of a memory cell differs according to the temperature. To account for this trait, a method of setting up and controlling a deciding voltage according to the temperature may be used.
To be specific, since the threshold voltage of a memory cell is lowered in a hot temperature condition and increased in a cold temperature condition, the deciding voltage for determining the type of distribution, that is, the first deciding voltage V_VF1 and the second deciding voltage V_VF2, should be set to different values. For example, the second deciding voltage V_VF2 corresponding to the cold temperature condition is set to be higher than the first deciding voltage V_VF1 corresponding to the hot temperature condition.
When the memory cell described above uses the ISPP, it takes a predetermined time, which is a programming time, for the memory cell to have the distribution of FIG. 1 based on the ISPP. The programming time is different according to the distribution of the memory cells, which may be different according to whether the memory cell is in the hot temperature state or the cold temperature state. In other words, for the same data, the programming time in the cold temperature condition is longer than the programming time in the cold temperature condition.